Electronic devices such as integrated circuits and passive electronic devices are packaged in a variety of configurations. One known configuration involves the formation of a solder ball array on the exterior of the package to provide electrical communication between the package device and other components such as a Printed Circuit Board (PCB) or test socket. In such solder ball packaging, a series of solder balls are adhered to conductive leads from the packaged device and spatially arranged in an array (e.g., a grid of perpendicular rows and columns) with a solder ball at the column and row intersections.
Methods for mounting chips and other semiconductor packages on substrates known as “flip-chip techniques,” in which the bottom surface of a die and a substrate are connected via bumps arranged in the form of an array, are conventionally well-known.
The current packaging trend is toward smaller form factors with higher chip integration into one chip module. This trend can issue design challenges for the routing in terms of substrate and assembly processes.